TiTe/Ge$_2$Sb$_2$Te$_5$ bi-layer-based Phase-Change Memory targeting storage class memory

G. Lama (1) , M. Bernard (1) , J. Garrione (1) , N. Bernier (1) , N. Castellani (1) , G. Bourgeois (1) , M.C. Cyrille (1) , F. Andrieu (1) , Gabriele Navarro (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

In this work, we introduce an innovative Phase-Change Memory (PCM) based on a TiTe and Ge$_2$Sb$_2$Te$_5$ (GST) bi-layer stack that presents low resistance variability since the out-of-fabrication in 4 kb array. It allows creating reliably an intermixed system right from the first programming in the active volume of the device. TiTe/GST PCM exhibits higher speed, lower variability of intermediate resistance states and lower drift compared to standard GST. An endurance of more than 10$^8$ cycles can be achieved and we found a reduced cycle-to-cycle variability even after endurance stress. Such new TiTe/GST stack, based on our results, demonstrates to be a valuable candidate for PCM targeting Storage Class Memory applications.

Domaines: Sciences de l'ingénieur [physics]

G. Lama, M. Bernard, J. Garrione, N. Bernier, N. Castellani, et al.. TiTe/Ge$_2$Sb$_2$Te$_5$ bi-layer-based Phase-Change Memory targeting storage class memory. ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Sep 2022, Milan, Italy. pp.237-240, ⟨10.1109/ESSDERC55479.2022.9947157⟩. ⟨cea-03927976⟩