Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

Marie-Line Pourteau (1) , Ahmed Gharbi (1) , Pierre Brianceau (1) , Jacques-Alexandre Dallery (2) , Fabien Laulagnet (1) , Guido Rademaker (1) , Raluca Tiron (1) , Hans-Juergen Engelmann (3) , Johannes von Borany (3) , Karl-Heinz Heinig (3) , Mathias Rommel (4) , Leander Baier (4)

1 DPFT - Département Plate-Forme Technologique
2 Vistec Electron Beam GmbH
3 HZDR - Helmholtz-Zentrum Dresden-Rossendorf
4 Fraunhofer IISB - Fraunhofer Institute for Integrated Systems and Device Technology

SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.

Mots clés: Single-electron-transistor; Multilayer nanopillars; Si nanodots; E-beam lithography; ICP-RIE; EFTEM

Domaines: Micro et nanotechnologies/Microélectronique

Marie-Line Pourteau, Ahmed Gharbi, Pierre Brianceau, Jacques-Alexandre Dallery, Fabien Laulagnet, et al.. Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration. Micro and Nano Engineering, 2020, 9, https://doi.org/10.1016/j.mne.2020.100074. ⟨10.1016/j.mne.2020.100074⟩. ⟨cea-03409432⟩