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Journal Articles Micro and Nano Engineering Year : 2020

Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

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Abstract

SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.
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Dates and versions

cea-03409432 , version 1 (29-10-2021)

Licence

Attribution - CC BY 4.0

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Cite

Marie-Line Pourteau, Ahmed Gharbi, Pierre Brianceau, Jacques-Alexandre Dallery, Fabien Laulagnet, et al.. Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration. Micro and Nano Engineering, 2020, 9, https://doi.org/10.1016/j.mne.2020.100074. ⟨10.1016/j.mne.2020.100074⟩. ⟨cea-03409432⟩
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