Stacked-Wires FETs for advanced CMOS scaling - Archive ouverte HAL Access content directly
Conference Papers Year :

Stacked-Wires FETs for advanced CMOS scaling

(1) , (1) , (2) , (1) , (1) , (1) , (1) , (1) , (2) , (1) , (1) , (1) , (1)
1
2

Abstract

We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
Fichier principal
Vignette du fichier
7-Barraud_SSDM2017.pdf (674.24 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

cea-01973414 , version 1 (08-01-2019)

Identifiers

  • HAL Id : cea-01973414 , version 1

Cite

S. Barraud, V. Lapras, M. Samson, B. Previtali, J M Hartmann, et al.. Stacked-Wires FETs for advanced CMOS scaling. 2017 International Conference on Solid State Devices and Materials (SSDM 2017), Sep 2017, Sendaï, Japan. ⟨cea-01973414⟩
163 View
226 Download

Share

Gmail Facebook Twitter LinkedIn More