Stacked-Wires FETs for advanced CMOS scaling

Abstract : We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
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Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:55 PM
Last modification on : Monday, February 25, 2019 - 4:34:22 PM
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S. Barraud, V. Lapras, M. Samson, B. Previtali, J Hartmann, et al.. Stacked-Wires FETs for advanced CMOS scaling. 2017 International Conference on Solid State Devices and Materials (SSDM 2017), Sep 2017, Sendaï, Japan. ⟨cea-01973414⟩

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