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Conference papers
Stacked-Wires FETs for advanced CMOS scaling
Abstract : We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
Cited literature [2 references]
https://hal-cea.archives-ouvertes.fr/cea-01973414
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:55 PM
Last modification on : Monday, April 6, 2020 - 9:22:34 AM
Document(s) archivé(s) le : Tuesday, April 9, 2019 - 4:10:02 PM
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:55 PM
Last modification on : Monday, April 6, 2020 - 9:22:34 AM
Document(s) archivé(s) le : Tuesday, April 9, 2019 - 4:10:02 PM
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7-Barraud_SSDM2017.pdf
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