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Stacked-Wires FETs for advanced CMOS scaling

S. Barraud 1, * V. Lapras 1 M. Samson 2 B. Previtali 1 J Hartmann 1 N. Rambal 1 C Vizioz 1 V. Loup 1 C. Comboroure 2 F. Triozon 1 N. Bernier 1 D. Cooper 1 M. Vinet 1
* Corresponding author
1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]
Abstract : We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
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Submitted on : Tuesday, January 8, 2019 - 12:05:55 PM
Last modification on : Thursday, June 11, 2020 - 5:04:08 PM
Long-term archiving on: : Tuesday, April 9, 2019 - 4:10:02 PM

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S. Barraud, V. Lapras, M. Samson, B. Previtali, J Hartmann, et al.. Stacked-Wires FETs for advanced CMOS scaling. 2017 International Conference on Solid State Devices and Materials (SSDM 2017), Sep 2017, Sendaï, Japan. ⟨cea-01973414⟩

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