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Conference papers
Stacked-Wires FETs for advanced CMOS scaling
S. Barraud
1, *
V. Lapras
1
M. Samson
2
B. Previtali
1
J Hartmann
1
N. Rambal
1
C Vizioz
1
V. Loup
1
C. Comboroure
2
F. Triozon
1
N. Bernier
1
D. Cooper
1
M. Vinet
1
S. Barraud 1
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Correspondent author
V. Lapras 1
Author
M. Samson 2
Author
B. Previtali 1
Author
M. Vinet 1
Author
1
CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)
- DRT (CEA) - Direction de Recherche Technologique (CEA) : DRT (France)
- CEA - Commissariat à l'énergie atomique et aux énergies alternatives : DRT (Centre de Saclay Centre de Grenoble Centre de Cadarache etc - France)
2
ST-CROLLES - STMicroelectronics [Crolles] (850 rue Jean Monnet BP 16 38926 Crolles - France)
Abstract : We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-01973414
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:55 PM
Last modification on : Thursday, June 11, 2020 - 5:04:08 PM
Document(s) archivé(s) le : Tuesday, April 9, 2019 - 4:10:02 PM
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:55 PM
Last modification on : Thursday, June 11, 2020 - 5:04:08 PM
Document(s) archivé(s) le : Tuesday, April 9, 2019 - 4:10:02 PM
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7-Barraud_SSDM2017.pdf
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- HAL Id : cea-01973414, version 1
Citation
S. Barraud, V. Lapras, M. Samson, B. Previtali, J Hartmann, et al.. Stacked-Wires FETs for advanced CMOS scaling. 2017 International Conference on Solid State Devices and Materials (SSDM 2017), Sep 2017, Sendaï, Japan. ⟨cea-01973414⟩
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