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High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders

Abstract : —This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance.
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https://hal-cea.archives-ouvertes.fr/cea-01567164
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Submitted on : Friday, July 21, 2017 - 7:00:45 PM
Last modification on : Thursday, June 11, 2020 - 5:04:06 PM

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Thien Truong Nguyen-Ly, Valentin Savin, Xavier Popon, David Declercq. High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders. 2017 IEEE International Conference on Communications Workshops (ICC Workshops), May 2017, Paris, France. pp.961 - 966, ⟨10.1109/ICCW.2017.7962783⟩. ⟨cea-01567164⟩

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