High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders

Thien Truong Nguyen-Ly (1, 2) , Valentin Savin (1) , Xavier Popon (1) , David Declercq (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ETIS - UMR 8051 - Equipes Traitement de l'Information et Systèmes

—This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance.

Domains: Engineering Sciences [physics]

Thien Truong Nguyen-Ly, Valentin Savin, Xavier Popon, David Declercq. High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders. 2017 IEEE International Conference on Communications Workshops (ICC Workshops), May 2017, Paris, France. pp.961 - 966, ⟨10.1109/ICCW.2017.7962783⟩. ⟨cea-01567164⟩