 |
Conference papers
High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders
Abstract : —This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance.
Cited literature [10 references]
https://hal-cea.archives-ouvertes.fr/cea-01567164
Contributor : Sylvie Mayrargue <>
Submitted on : Friday, July 21, 2017 - 7:00:45 PM
Last modification on : Tuesday, December 8, 2020 - 9:59:34 AM
Contributor : Sylvie Mayrargue <>
Submitted on : Friday, July 21, 2017 - 7:00:45 PM
Last modification on : Tuesday, December 8, 2020 - 9:59:34 AM
File
17-ICC_High Throughput FPGA Im...
Files produced by the author(s)