High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders

Abstract : —This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance.
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Communication dans un congrès
2017 IEEE International Conference on Communications Workshops (ICC Workshops), May 2017, Paris, France. Proceedings of the IEEE International Conference on Communications (ICC) 2017, pp.961 - 966, 2017, 〈10.1109/ICCW.2017.7962783〉
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Soumis le : vendredi 21 juillet 2017 - 19:00:45
Dernière modification le : jeudi 14 septembre 2017 - 13:45:36

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Thien Truong Nguyen-Ly, Valentin Savin, Xavier Popon, David Declercq. High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders. 2017 IEEE International Conference on Communications Workshops (ICC Workshops), May 2017, Paris, France. Proceedings of the IEEE International Conference on Communications (ICC) 2017, pp.961 - 966, 2017, 〈10.1109/ICCW.2017.7962783〉. 〈cea-01567164〉

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