Improvement of the Tolerated Raw Bit Error Rate in NAND Flash-based SSDs with Selective Refresh

Emna Farjallah (1) , Jean-Marc Armani (1) , Valentin Gherman (1) , Luigi Dilillo (2)

1 LFIC (CEA, LIST) - Laboratoire Fiabilité et Intégration de Capteurs (CEA, LIST)
2 TEST - Test and dEpendability of microelectronic integrated SysTems

A recent large-scale study revealed that the uncorrectable bit error rates in data center solid-sate drives (SSDs) may fall far below the JEDEC standard recommendations. Here, a new refresh policy is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small ratio of SSD units may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. An approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed or refreshed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next page access is an indication that data needs to be refreshed. It is estimated that the tolerated retention RBER can be increased by up to 35× over a storage period of 3 years if the stored data are checked on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. Maximum refresh time reductions of about 12× are reported as compared to systematic refresh schemes.

Mots clés: Adaptability; Bit error rate; Data retention; data storage time; NAND flash; flash memory; SSD; Reliability; instrumentation

Domaines: Micro et nanotechnologies/Microélectronique; Instrumentations et Détecteurs [physics.ins-det]

Emna Farjallah, Jean-Marc Armani, Valentin Gherman, Luigi Dilillo. Improvement of the Tolerated Raw Bit Error Rate in NAND Flash-based SSDs with Selective Refresh. Microelectronics Reliability, 2019, 96, pp.37-45. ⟨10.1016/j.microrel.2019.01.014⟩. ⟨lirmm-02008002⟩