Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory computing with up to 16 parallel operations

Eduardo Esmanhotto (1) , T. Hirtzlin (1) , N. Castellani (1) , S. Martin (1) , B. Giraud (2) , F. Andrieu (1) , J F Nodin (1) , D. Querlioz (3) , J-M. Portal (4) , E. Vianello (1)

1 DCOS - Département Composants Silicium
2 LFIM - Laboratoire Fonctions Innovantes pour circuits Mixtes
3 C2N - Centre de Nanosciences et de Nanotechnologies
4 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence

Crossbar arrays of resistive memories (RRAM) hold the promise of enabling In-Memory Computing (IMC), but essential challenges due to the impact of device imperfection and device endurance have yet to be overcome. In this work, we demonstrate experimentally an RRAM-based IMC logic concept with strong resilience to RRAM variability, even after one million endurance cycles. Our work relies on a generalization of the concept of in-memory Scouting Logic, and we demonstrate it experimentally with up to 16 parallel devices (operands), a new milestone for RRAM in-memory logic. Moreover, we combine IMC with Multi-Level-Cell programming and demonstrate experimentally, for the first time, an IMC RRAM-based MLC 2-bit adder.

Domaines: Micro et nanotechnologies/Microélectronique

Eduardo Esmanhotto, T. Hirtzlin, N. Castellani, S. Martin, B. Giraud, et al.. Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory computing with up to 16 parallel operations. IRPS 2022 - IEEE International Reliability Physics Symposium, Mar 2022, Dallas, United States. pp.P8-1-P8-4, ⟨10.1109/IRPS48227.2022.9764474⟩. ⟨hal-04442653⟩