Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits

P. Sideris (1, 2) , L. Brunet (2) , L. Ciampolini (3) , G. Sicard (4) , P. Batude (2) , Christoforos Theodorou (1)

1 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
2 DCOS - Département Composants Silicium
3 LFIM - Laboratoire Fonctions Innovantes pour circuits Mixtes
4 DOPT - Département d'Optronique

This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

Domaines: Micro et nanotechnologies/Microélectronique; Electronique

P. Sideris, L. Brunet, L. Ciampolini, G. Sicard, P. Batude, et al.. Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits. Solid-State Electronics, 2020, 168, pp.107715. ⟨10.1016/j.sse.2019.107715⟩. ⟨hal-03089143⟩