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F. Blanc, Etude d'un nouveau concept de calculateur reconfigurable : architecture et outils, 2002.

N. Ventroux, F. Blanc, and D. Lavenier, A Low Complex Scheduling Algorithm for Multi-Processor System-on-Chip, 23 rd IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'05), 2005.

N. Ventroux, S. Chevobbe, F. Blanc, and T. Collette, An Auto-adaptative Reconfigurable Architecture for the Control, th Asia-Pacific Computer Systems Architecture Conference Springer-Verlag LNCS 3189, pp.72-87, 2004.
DOI : 10.1007/978-3-540-30102-8_7
URL : https://hal.archives-ouvertes.fr/cea-01789447

S. Chevobbe, N. Ventroux, F. Blanc, and T. Collette, RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems, 3 rd International Workshop on Computer Systems, Architectures, Modeling and Simulation (SAMOS'03), Springer-Verlag LNCS 3133, pp.20-29, 2003.
DOI : 10.1007/978-3-540-27776-7_3

N. Ventroux, J. F. Nezan, M. Raulet, and O. Déforges, Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogeneous architecture, IEEE International Conference on Accoustics, Speech and Signal Processing, 2003.
URL : https://hal.archives-ouvertes.fr/hal-00125123

R. David, V. David, N. Ventroux, and T. Collette, Procédé et système de calcul intensif multitâche et multiflot en temps réel, 2005.

N. Ventroux, S. Chevobbe, F. Blanc, and T. Collette, Procédé d'ordonnancement de traitement de tâches et dispositif pour mettre en oeuvre le procédé, 2004.

N. Ventroux, RAMPASS : état d'avancement (mise à jour) Rapport interne, CEA LIST, 2004.

N. Ventroux, RAMPASS : état d'avancement. Rapport interne, CEA LIST, 2003.