Skip to Main content Skip to Navigation
Journal articles

Error Correction Improvement based on Weak-Bit-Flipping for Resistive Memories

Abstract : Resistive memories are affected by significant error rates tied to structural relaxation and wear out of the resistive memory devices. A way to reduce the need for strong errorcorrecting codes (ECCs) is to improve error correction based on the weak bits, i.e., potentially faulty bits, identified in sensed memory words. Here, it is formally proven that conventional ECC decoders reinforced with weak-bit-flipping may achieve similar error correction capability as theoretical generalized minimum-distance decoders. It is shown that weak-bit-flipping may reduce the uncorrectable bit error rate (UBER) by orders of magnitude when applied in conjunction with single-errorcorrecting and double-error-detecting (SEC-DED) or double error-correcting and triple-error-detecting (DEC-TED) codes. In particular, weak-bit-information extracted from a 2T2R memory and used to reinforce a DEC-TED code with a conventional decoder may enable an UBER that is one order of magnitude better than the UBER achieved with a triple-errorcorrecting (TEC) code and a conventional decoder.
Document type :
Journal articles
Complete list of metadata
Contributor : Contributeur MAP CEA Connect in order to contact the contributor
Submitted on : Thursday, August 25, 2022 - 12:02:59 PM
Last modification on : Sunday, August 28, 2022 - 3:21:30 AM


 Restricted access
To satisfy the distribution rights of the publisher, the document is embargoed until : 2024-08-24

Please log in to resquest access to the document



Valentin Gherman, Lorenzo Ciampolini, Samuel Evain, Sébastien Ricavy. Error Correction Improvement based on Weak-Bit-Flipping for Resistive Memories. Microelectronics Reliability, Elsevier, 2022, 136, pp.1-10. ⟨10.1016/j.microrel.2022.114669⟩. ⟨cea-03760496⟩



Record views