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Conference Papers Year : 2022

Work in Progress: Automatic Construction ofPipeline Datapaths from High-Level HDL Code

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Abstract

Safety-critical systems rely on worst-case timing analysis under architecture considerations to ensure that their timing bounds could be guaranteed. Usually, such architecture models are constructed by hand, from processor manuals. However, with open hardware initiatives and high-level Hardware Description Languages (HDL), automation would and should be possible. In this paper, we present an approach for constructing pipeline datapath models from processor designs described in high-level HDLs. We propose a methodology based on the Chisel/FIRRTL Hardware Compiler Framework and we report preliminary results on several open-source RISC-V processors.
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Dates and versions

cea-03759799 , version 1 (24-08-2022)

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  • HAL Id : cea-03759799 , version 1

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Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan. Work in Progress: Automatic Construction ofPipeline Datapaths from High-Level HDL Code. 28th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2022), IEEE, May 2022, Milan, Italy. pp.4. ⟨cea-03759799⟩
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