Skip to Main content Skip to Navigation
Conference papers

Work in Progress: Automatic Construction ofPipeline Datapaths from High-Level HDL Code

Samira Ait Bensaid 1 Mihail Asavoae 1 Farhat Thabet 1 Mathieu Jan 1 
1 LECA - Laboratoire Environnement de Conception & Architecture
Université Paris-Saclay, DSCIN - Département Systèmes et Circuits Intégrés Numériques : DRT/LIST/DSCIN
Abstract : Safety-critical systems rely on worst-case timing analysis under architecture considerations to ensure that their timing bounds could be guaranteed. Usually, such architecture models are constructed by hand, from processor manuals. However, with open hardware initiatives and high-level Hardware Description Languages (HDL), automation would and should be possible. In this paper, we present an approach for constructing pipeline datapath models from processor designs described in high-level HDLs. We propose a methodology based on the Chisel/FIRRTL Hardware Compiler Framework and we report preliminary results on several open-source RISC-V processors.
Complete list of metadata

https://hal-cea.archives-ouvertes.fr/cea-03759799
Contributor : Contributeur MAP CEA Connect in order to contact the contributor
Submitted on : Wednesday, August 24, 2022 - 3:00:25 PM
Last modification on : Sunday, August 28, 2022 - 3:21:26 AM

File

RTAS_2022__paper_version_final...
Files produced by the author(s)

Identifiers

  • HAL Id : cea-03759799, version 1

Citation

Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan. Work in Progress: Automatic Construction ofPipeline Datapaths from High-Level HDL Code. 28th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2022), IEEE, May 2022, Milan, Italy. pp.4. ⟨cea-03759799⟩

Share

Metrics

Record views

38

Files downloads

2