Multilevel simulation-based co-design of next generation HPC microprocessors

Lilia Zaourar (1) , Mohamed Benazouz (1) , Ayoub Mouhagir (1) , Fatma Jebali (1) , Tanguy Sassolas (1) , Jean-Christophe Weill (1) , Carlos Falquez (2) , Nam Ho (2) , Dirk Pleiter (2) , Antoni Portero (2) , Estela Suarez (2) , Polydoros Petrakis (3) , Vassilis Papaefstathiou (3) , Manolis Marazakis (3) , Milan Radulovic (4) , Francesc Martinez (4) , Adrià Armejach (4) , Marc Casas (4) , Alejandro Nocua , Romain Dolbeau

1 LECA - Laboratoire Environnement de Conception & Architecture
2 JSC - Jülich Supercomputing Centre
3 Institute of Computer Science - ICS (Heraklion, Greece)
4 BSC-CNS - Barcelona Supercomputing Center - Centro Nacional de Supercomputacion

This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-level cache (SLC) size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable sufficient accuracy without having to resort to highly detailed simulations. Then we apply gem5, a cycle-accurate micro-architecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study the network-on-chip (NoC) topology and IP placements using both gem5 for representative small- to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details. Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings. We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns and evaluate them to guide architectural design and optimization decisions. Performance analysis is carried out with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SIMD instruction width, SLC sizing, memory bandwidth as well as the best placement of memory controllers and NoC form factor. Thus, we provide critical insights for efficient design of future HPC microprocessors.

Mots clés: Co-design; Simulation; Emulation; Benchmarking; HPC

Domaines: Modélisation et simulation; Architectures Matérielles [cs.AR]; Systèmes embarqués

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, et al.. Multilevel simulation-based co-design of next generation HPC microprocessors. 2021 International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), Nov 2021, St. Louis, United States. pp.18, ⟨10.1109/PMBS54543.2021.00008⟩. ⟨cea-03605097⟩