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A 35.6 TOPS/W/mm2 3-Stage Pipelined Computational SRAM With Adjustable Form Factor for Highly Data-Centric Applications

Jean-Philippe Noel Noel 1 Manuel Pezzin 1 Roman Gauchi 1 Jean-Frédéric Christmann 1 Maha Kooli 1 Henri-Pierre Charles 1 Lorenzo Ciampolini 1 Mariam Diallo 1 Florent Lepin 1 Benjamin Blampey 2 Pascal Vivet 1 Subhasish Mitra 3 Bastien Giraud 1 
1 LFIM - Laboratoire Fonctions Innovantes pour circuits Mixtes
UGA - Université Grenoble Alpes, DSCIN - Département Systèmes et Circuits Intégrés Numériques : DRT/LIST/DSCIN
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 Stanford University
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https://hal-cea.archives-ouvertes.fr/cea-03605066
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Submitted on : Thursday, March 10, 2022 - 6:00:10 PM
Last modification on : Sunday, March 13, 2022 - 3:26:18 AM

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Jean-Philippe Noel Noel, Manuel Pezzin, Roman Gauchi, Jean-Frédéric Christmann, Maha Kooli, et al.. A 35.6 TOPS/W/mm2 3-Stage Pipelined Computational SRAM With Adjustable Form Factor for Highly Data-Centric Applications. IEEE Journal of Solid-State Circuits, 2020, 2, pp.286-298. ⟨10.1109/LSSC.2020.3010377⟩. ⟨cea-03605066⟩

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