Binary linear ECCs optimized for bit inversion in memories with asymmetric error probabilities

Valentin Gherman (1) , Samuel Evain (2) , Bastien Giraud (1, 3)

1 LFIM - Laboratoire Fonctions Innovantes pour circuits Mixtes
2 DSCIN (CEA, LIST) - Département Systèmes et Circuits Intégrés Numériques
3 DACLE-LETI - Département d'Architectures, Conception et Logiciels Embarqués-LETI

Many memory types are asymmetric with respect to the error vulnerability of stored 0's and 1's. For instance, DRAM, STT-MRAM and NAND flash memories may suffer from asymmetric error rates. A recently proposed errorprotection scheme consists in the inversion of the memory words with too many vulnerable values before they are stored in an asymmetric memory. In this paper, a method is proposed for the optimization of systematic binary linear block error-correcting codes in order to maximize their impact when combined with memory word inversion.

Mots clés: memory word inversion; asymmetric error rates

Domaines: Performance et fiabilité [cs.PF]

Valentin Gherman, Samuel Evain, Bastien Giraud. Binary linear ECCs optimized for bit inversion in memories with asymmetric error probabilities. DATE 2020 - 2020 Design, Automation & Test in Europe Conference & Exhibition, IEEE, Mar 2020, Grenoble, France. pp.298-301, ⟨10.23919/DATE48585.2020.9116531⟩. ⟨cea-03469725⟩