Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator
Résumé
In-Memory Computing (IMC) is a promising paradigm to mitigate the von Neumann bottleneck. However its evaluation on complete applications in the context of full-scale systems is limited by the complexity of simulation frameworks as well is the disjunction between hardware exploration and compiler support.
This paper proposes a global exploration flow in the scale of Instruction Set Architectures (ISA) to perform both modeling and the generation of compiler support to perform ISAlevel exploration. Our emulation methodology is based on QEMU and allows the modeling of cache hierarchies, while our compiler support is automatically generated and based on a specialized compiler.
We evaluate three applications in the domains of image processing and linear algebra on a reference IMC architecture, and analyze the obtained results to validate our methodology.
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