Gate spacers etching of Si$_3$N$_4$ using cyclic approach for 3D CMOS devices

Valentin Bacquie (1) , Aurelien Tavernier (1) , Francois Boulard (1) , Olivier Pollet (1) , Nicolas Posseme (1)

1 DPFT - Département Plate-Forme Technologique

In this work, we optimize a CH$_3$F/O$_2$/He/SiCl$_4$ chemistry to etch silicon nitride gate spacers for 3D CMOS devices in a 300mm inductively coupled plasma reactor. The chemistry has high directivity and high selectivity to Si and SiO$_2$. A cyclic approach, which alternates this chemistry with a CH$_2$F$_2$/O$_2$/CH$_4$/He plasma, is investigated. Using $quasi\ in\ situ$ x-ray photoelectron spectroscopy and ellipsometry measurements, etching mechanisms are proposed to explain the results obtained. As a result of process optimization, silicon nitride spacers with vertical profile and a small critical dimension loss of 3 nm as well as complete spacers removal on sidewalls of the active area are obtained on 3D patterns, confirming the advantages of this approach.

Domaines: Electronique; Génie des procédés; Matériaux; Plasmas

Valentin Bacquie, Aurelien Tavernier, Francois Boulard, Olivier Pollet, Nicolas Posseme. Gate spacers etching of Si$_3$N$_4$ using cyclic approach for 3D CMOS devices. Journal of Vacuum Science & Technology A, 2021, 39, pp.033005. ⟨10.1116/6.0000871⟩. ⟨cea-03343549⟩