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M3D-ADTCO: Monolithic 3D architecture, design and technology co-optimization for high energy efficient 3D IC

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Abstract

Monolithic 3D (M3D) stands now as the ultimate technology to side step Moore's Law stagnation. Due to its nanoscale Monolithic Inter-tier Via (MIV), M3D enables an ultrahigh density interconnect between Logic and Memory that is required in the field of highly energy efficient 3D integrated circuits (3D-ICs) designed for new abundant data computing systems. At design level, M3D still suffers from a lack of commercial tools, especially for Place and Route, precluding the capability to provide signoff M3D GDS. In this paper, we introduce M3D-ADTCO, an architecture, design and technology co-optimization platform aimed at providing signoff M3D GDS. It relies on a M3D Process Design Kit and the use of a commercial Place and Route tool. We demonstrate an area reduction of 23.61 % at iso performance and power compared to a 2D RISC-V micro-controller based System on Chip (SoC) while creating space to increase (2x) the RISC-V instruction memory.
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Dates and versions

cea-03288836 , version 1 (16-07-2021)

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Cite

Sebastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, et al.. M3D-ADTCO: Monolithic 3D architecture, design and technology co-optimization for high energy efficient 3D IC. 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1740-1745, ⟨10.23919/DATE48585.2020.9116293⟩. ⟨cea-03288836⟩
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