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Journal Articles IEEE Transactions on Computers Year : 2021

A RISC-V ISA extension for ultra-low power IoT wireless signal processing

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Abstract

This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to come at a near-zero energy cost. Both an instruction accurate (IA) and a cycle accurate (CA) model of the new architecture are used to evaluate six IoT baseband processing test benches including FSK demodulation and LoRa preamble detection. Simulation results show cycle count improvements from 19% to 68%. Post synthesis simulations for a target 22nm FD-SOI technology show less than 1% power and 28% area overheads, respectively, relative to a baseline RV32IM design. Power simulations show a peak power consumption of 380 µW for Bluetooth LE demodulation and 225 µW for LoRa preamble detection (BW = 500 kHz, SF = 11).
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Dates and versions

cea-03158876 , version 1 (04-03-2021)
cea-03158876 , version 2 (17-03-2021)

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Hela Belhadj Amor, Carolynn Bernier, Zdenek Prikryl. A RISC-V ISA extension for ultra-low power IoT wireless signal processing. IEEE Transactions on Computers, 2021, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩. ⟨cea-03158876v2⟩
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