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# Innovative Low-Power Self-Nanoconfined Phase-Change Memory

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Abstract : In this paper, we demonstrate at array level and in industrial like devices, the extreme scaling down to nanometric dimensions of the Phase-Change Memory technology thanks to an innovative Self-Nano-Confined PCM device (SNC PCM). We show how such solution based on an optimized GeN/GeSbTe stack enables programming down to 50 $\mu$A and endurance up to more than 10$^8$ cycles in 4 kb arrays, with the huge advantage of having no dependency on the critical lithography dimension used. We further demonstrate that the high thermal confinement achieved in such extremely confined PCM makes the engineering of the SET pulse becoming fundamental in order to assure a reduced SET resistance drift. Moreover, thanks to physico-chemical analyses and 3D TCAD electro-thermal simulations we demonstrate the Self-Nano-Confined phenomenon, revealing an effective scaling of the PCM down to around 12 nm and how it improves the thermal efficiency of the device thanks to a reduced current density and thermal stress in the system.
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Journal articles

https://hal-cea.archives-ouvertes.fr/cea-03119677
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Submitted on : Monday, January 25, 2021 - 8:15:02 AM
Last modification on : Friday, April 1, 2022 - 3:46:22 AM
Long-term archiving on: : Monday, April 26, 2021 - 6:31:19 PM

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TED_ALSerra_022021_v2.pdf
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### Citation

Anna Lisa Serra, Gauthier Lefevre, Guillaume Bourgeois, Chiara Sabbione, Niccolo Castellani, et al.. Innovative Low-Power Self-Nanoconfined Phase-Change Memory. IEEE Transactions on Electron Devices, 2021, 68 (2), pp.535-540. ⟨10.1109/TED.2020.3044267⟩. ⟨cea-03119677⟩

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