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Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization

Abstract : For big data applications, bringing computation to the memory is expected to reduce drastically data transfers, which can be done using recent concepts of Computing-In-Memory (CIM). To address kernels with larger memory data sets, we propose a reconfigurable tile-based architecture composed of Computational-SRAM (C-SRAM) tiles, each enabling arithmetic and logic operations within the memory. The proposed horizontal scalability and vertical data communication are combined to select the optimal vector width for maximum performance. These schemes allow to use vector-based kernels available on existing SIMD engines onto the targeted CIM architecture. For architecture exploration, we propose an instruction-accurate simulation platform using SystemC/TLM to quantify performance and energy of various kernels. For detailed performance evaluation, the platform is calibrated with data extracted from the Place&Route C-SRAM circuit, designed in 22nm FDSOI technology. Compared to 512-bit SIMD architecture, the proposed CIM architecture achieves an EDP reduction up to 60× and 34× for memory bound kernels and for compute bound kernels, respectively.
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https://hal-cea.archives-ouvertes.fr/cea-02963719
Contributor : Roman Gauchi <>
Submitted on : Sunday, October 11, 2020 - 2:37:26 PM
Last modification on : Tuesday, October 13, 2020 - 11:08:02 AM

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Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noel, Bastien Giraud, et al.. Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. ISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design, Aug 2020, Boston, MA, United States. pp.121-126, ⟨10.1145/3370748.3406550⟩. ⟨cea-02963719⟩

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