Computing's Energy Problem (and what we can do about it), ISSCC, pp.10-14, 2014. ,
Computer Architecture: A Quantitative Approach, 2018. ,
In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array, JSSC, vol.52, issue.4, pp.915-924, 2017. ,
Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security, JSSC, vol.53, issue.4, pp.995-1005, 2018. ,
A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration, pp.224-226, 2019. ,
Exploration of a Scalable Vector-based In-Memory Computing Architecture via a System-on-Chip Evaluation Framework, 2020. ,
, Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces, 2018.
URL : https://hal.archives-ouvertes.fr/cea-01757665
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture, 2019. ,
URL : https://hal.archives-ouvertes.fr/cea-02399937
2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes, IEDM, pp.269-272, 2015. ,
5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology, JSSC, vol.52, issue.1, pp.229-239, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01891216
A 4R2W Register File for a 2.3GHz Wire-Speed POWER Processor with Double-Pumped Write Operation, ISSCC, pp.256-257, 2011. ,
A Configurable 2-in-1 SRAM Compiler with Constant-Negative-Level Write Driver for Low Vmin in 16nm Fin-FET CMOS, pp.145-148, 2014. ,
A 6.05-Mb/mm² 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time, 2016. ,
A 5.92-Mb/mm² 28-nm Pseudo 2-Read/Write Dual-port SRAM using Double Pumping Circuitry, pp.17-20, 2016. ,
An Ultra High Density Pseudo Dual-Port SRAM in 16nm FINFET Process for Graphics Processors, SOCC, pp.12-17, 2017. ,
A 7nm Double-Pumped 6R6W Register File for Machine Learning Memory, pp.15-16, 2018. ,