Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing

J.-P Noel (1) , Valentin Egloff (1) , M. Kooli (1) , R. Gauchi (1) , J.-M. Portal (2) , H.-P Charles (3) , P. Vivet (4) , B. Giraud (1)

1 LFIM - Laboratoire Fonctions Innovantes pour circuits Mixtes
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 CEA - Commissariat à l'énergie atomique et aux énergies alternatives
4 DSCIN (CEA, LIST) - Département Systèmes et Circuits Intégrés Numériques

This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and a configurable RTL IP. The main goal is to drastically reduce the development effort compared to a full-custom design, while offering a flexibility of use and a high-yield production. The proposed C-SRAM architecture has been developed to process energy-efficient vector data coupled with a scalar processor, while limiting the data transfer on the system bus. The results obtained by post P&R simulations show that 2RW and 4RW C-SRAM configurations using the double pumping technique achieved the highest performance to process vectorized MAC operations compared to the others configurations. Moreover, it has been shown that the impact of the digital wrapper decoding and executing the instructions can be mitigated by increasing the memory cut size to represent less than 10% in area and 20% in power consumption.

Domaines: Systèmes embarqués

J.-P Noel, Valentin Egloff, M. Kooli, R. Gauchi, J.-M. Portal, et al.. Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1187-1192, ⟨10.23919/DATE48585.2020.9116506⟩. ⟨cea-02889406⟩