Analysis and characterization of inherent application resilience for approximate computing, Proc. DAC 2013, pp.1-9 ,
Approximate computing: A survey, IEEE Design & Test, vol.33, issue.1, pp.8-22, 2016. ,
A comparative review and evaluation of approximate adders, Proc. GLSVLSI 2015, pp.343-348 ,
Low-power high-speed multiplier for error-tolerant application, Proc. EDSSC, pp.1-4, 2010. ,
A methodology for energy-quality tradeoff using imprecise hardware, Proc. DAC 2012, pp.504-509 ,
New approximate multiplier for low power digital signal processing, Proc. CADS 2013, pp.25-30 ,
Synthesizing parsimonious inexact circuits through probabilistic design techniques, ACM Trans. Embed. Comput. Syst, vol.12, issue.2s, p.26, 2013. ,
Variable latency speculative addition: A new paradigm for arithmetic circuit design, Proc. DATE, pp.1250-1255, 2008. ,
Accuracy-configurable adder for approximate arithmetic designs, Proc. DAC 2012, pp.820-825 ,
A flexible low power dsp with a programmable truncated multiplier, IEEE Trans. on CAS I, vol.59, issue.11, pp.2555-2568, 2012. ,
On reconfiguration-oriented approximate adder design and its application, Proc. ICCAD 2013, pp.48-54 ,
Design of voltage-scalable meta-functions for approximate computing, Proc. DATE, pp.1-6, 2011. ,
A low-power, high-performance approximate multiplier with configurable partial error recovery, Proc. DATE, vol.95, p.4, 2014. ,
Dvas: Dynamic voltage accuracy scaling for increased energy-efficiency in approximate computing, Proc. ISLPED 2015, pp.237-242 ,
Slack redistribution for graceful degradation under voltage overscaling, Proc. ASP-DAC 2010, pp.825-831 ,
A survey on low-power techniques with emerging technologies: From devices to systems, J. Emerg. Technol. Comput. Syst, vol.12, issue.2, pp.1-12, 2015. ,
A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking, IEEE Journal of Solid-State Circuits, vol.50, issue.1, pp.125-136, 2015. ,
Architecting Voltage Islands in Core-based System-on-achip Designs, Proc. ISLPED, pp.180-185, 2004. ,
Regularity Driven Logic Synthesis, Proc. ICCAD, pp.439-446, 2000. ,
Clustered Voltage Scaling Technique for Low-power Design, Proc. ISLPED, pp.3-8, 1995. ,