V. Chippa, Analysis and characterization of inherent application resilience for approximate computing, Proc. DAC 2013, pp.1-9

Q. Xu, N. S. Kim, and T. Mytkowicz, Approximate computing: A survey, IEEE Design & Test, vol.33, issue.1, pp.8-22, 2016.

H. Jiang, J. Han, and F. Lombardi, A comparative review and evaluation of approximate adders, Proc. GLSVLSI 2015, pp.343-348

K. Y. Kyaw, W. L. Goh, and K. S. Yeo, Low-power high-speed multiplier for error-tolerant application, Proc. EDSSC, pp.1-4, 2010.

J. Huang, J. Lach, and G. Robins, A methodology for energy-quality tradeoff using imprecise hardware, Proc. DAC 2012, pp.504-509

F. Farshchi, M. S. Abrishami, and S. M. Fakhraie, New approximate multiplier for low power digital signal processing, Proc. CADS 2013, pp.25-30

A. Lingamneni, Synthesizing parsimonious inexact circuits through probabilistic design techniques, ACM Trans. Embed. Comput. Syst, vol.12, issue.2s, p.26, 2013.

A. Verma, P. Brisk, and P. Ienne, Variable latency speculative addition: A new paradigm for arithmetic circuit design, Proc. DATE, pp.1250-1255, 2008.

A. Kahng and S. Kang, Accuracy-configurable adder for approximate arithmetic designs, Proc. DAC 2012, pp.820-825

M. De-la-guia, W. Solaz, R. Han, and . Conway, A flexible low power dsp with a programmable truncated multiplier, IEEE Trans. on CAS I, vol.59, issue.11, pp.2555-2568, 2012.

R. Ye, On reconfiguration-oriented approximate adder design and its application, Proc. ICCAD 2013, pp.48-54

D. Mohapatra, Design of voltage-scalable meta-functions for approximate computing, Proc. DATE, pp.1-6, 2011.

C. Liu, J. Han, and F. Lombardi, A low-power, high-performance approximate multiplier with configurable partial error recovery, Proc. DATE, vol.95, p.4, 2014.

B. Moons and M. Verhelst, Dvas: Dynamic voltage accuracy scaling for increased energy-efficiency in approximate computing, Proc. ISLPED 2015, pp.237-242

A. Kahng, Slack redistribution for graceful degradation under voltage overscaling, Proc. ASP-DAC 2010, pp.825-831

P. Gaillardon, A survey on low-power techniques with emerging technologies: From devices to systems, J. Emerg. Technol. Comput. Syst, vol.12, issue.2, pp.1-12, 2015.

E. Beigné, A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking, IEEE Journal of Solid-State Circuits, vol.50, issue.1, pp.125-136, 2015.

J. Hu, Architecting Voltage Islands in Core-based System-on-achip Designs, Proc. ISLPED, pp.180-185, 2004.

T. Kutzschebauch and L. Stok, Regularity Driven Logic Synthesis, Proc. ICCAD, pp.439-446, 2000.

K. Usami and M. Horowitz, Clustered Voltage Scaling Technique for Low-power Design, Proc. ISLPED, pp.3-8, 1995.