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Conference Papers Year : 2017

A methodology for the design of dynamic accuracy operators by runtime back bias

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Abstract

Mobile and IoT applications must balance increasing processing demands with limited power and cost budgets. Approximate computing achieves this goal leveraging the error tolerance features common in many emerging applications to reduce power consumption. In particular, adequate (i.e., energy/qualityconfigurable) hardware operators are key components in an error tolerant system. Existing implementations of these operators require significant architectural modifications, hence they are often design-specific and tend to have large overheads compared to accurate units. In this paper, we propose a methodology to design adequate datapath operators in an automatic way, which uses threshold voltage scaling as a knob to dynamically control the power/accuracy tradeoff. The method overcomes the limitations of previous solutions based on supply voltage scaling, in that it introduces lower overheads and it allows fine-grain regulation of this tradeoff. We demonstrate our approach on a state-of-the-art 28nm FDSOI technology, exploiting the strong effect of back biasing on threshold voltage. Results show a power consumption reduction of as much as 39% compared to solutions based only on supply voltage scaling, at iso-accuracy
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Dates and versions

cea-02195002 , version 1 (26-07-2019)

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Jahier Pagliari, Daniele ; Durand, Yves ; Coriat, David ; Molnos, Anca ; Beigne, et al.. A methodology for the design of dynamic accuracy operators by runtime back bias. 2017 Design, Automation & Test in Europe Conference & Exhibition, IEEE, Mar 2017, lausanne, Switzerland. pp.1165-1170, ⟨10.23919/DATE.2017.7927165⟩. ⟨cea-02195002⟩
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