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1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell

Abstract : Content addressable memory (CAM) performs parallel data search at the cost of high area and power penalty. We propose a high-speed 6T-ReCSAM (Reconfigurable CAM/SRAM) with new energy efficient sensing technique. Proposed implementation is compatible with compact 6T-SRAM foundry bitcells. Test-macro of 8Kb is implemented in 28nm FDSOI CMOS and reaches up to 1.56GHz at 0.9V with 0.13fJ/bit energy consumption per search, giving an improvement of 4.6x [2], 8.3x [3], 5.9x [4] and 14.3x [5] with respect to Ref. [2]-[5]. Similarly, the search speed is improved by 4.2x [2], 3.12x [4], and 6.24x [5].
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https://hal-cea.archives-ouvertes.fr/cea-02194567
Contributor : Bruno Savelli <>
Submitted on : Thursday, July 25, 2019 - 4:18:24 PM
Last modification on : Thursday, June 11, 2020 - 5:04:09 PM

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Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel. 1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell. ESSCIRC 2017 - 43rd IEEE European Solid-State Circuits Conference, Sep 2017, Leuven, Belgium. pp.316-319, ⟨10.1109/ESSCIRC.2017.8094589⟩. ⟨cea-02194567⟩

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