In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization

Ivan Miro-Panades (1) , Edith Beigné (1) , Olivier Billoint (1) , Yvain Thonnart (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

Achieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circuit is presented which significantly minimizes the operating voltage and tracks it during run-time operation of a circuit without failure. A DSP core embedding this technique has been fabricated and measured. Its V$_{min}$ has been estimated within +3.5%/-2.5% at nominal clock frequency (1600MHz), thus reducing by 19% its energy per operation.

Mots clés: Design margins reduction; in-situ monitors; TMFLT

Domaines: Sciences de l'ingénieur [physics]

Ivan Miro-Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart. In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), IEEE, Jul 2017, Thessaloniki, Greece. pp.96-99, ⟨10.1109/IOLTS.2017.8046240⟩. ⟨cea-02194423⟩