High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

Reda Boumchedda; Jean-Philippe Noel; Bastien Giraud; Kaya Can Akyel; Mélanie Brocard; David Turgis; Edith Beigne

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

Reda Boumchedda ^{1, 2, *} Jean-Philippe Noel ² Bastien Giraud ² Kaya Can Akyel ² Mélanie Brocard ² David Turgis ¹ Edith Beigne ²

* Corresponding author

1 ST-CROLLES - STMicroelectronics [Crolles]

2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information

Abstract : In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted-silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the post-layout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node.

Document type :

Journal articles

Domain :

Engineering Sciences [physics]

Complete list of metadatas

https://hal-cea.archives-ouvertes.fr/cea-02193602
Contributor : Bruno Savelli <>
Submitted on : Wednesday, July 24, 2019 - 3:39:51 PM
Last modification on : Sunday, July 28, 2019 - 1:04:27 AM

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

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High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

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