Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell V$_T$-mixing

Abstract : We propose an original Technology/Design Cooptimization of standard cells mixing devices of different threshold voltages (VT-flavors) within a cell. It is successfully applied with nMOS Low-V$_T$ (LVT) and pMOS Super-Low-VT (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted SiliconOn-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the V$_T$ of pMOS subject to SiGechannel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and VDD=0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at V$_{DD}$=0.4V and FBB=1.6V and improves the energy efficiency with a -13% minimum Energy Delay Product (EDP) along with a 50mV V$_{DD}$ reduction at the minimum EDP
Document type :
Conference papers
Complete list of metadatas

https://hal-cea.archives-ouvertes.fr/cea-02188622
Contributor : Bruno Savelli <>
Submitted on : Thursday, July 18, 2019 - 4:12:24 PM
Last modification on : Saturday, July 20, 2019 - 1:25:33 AM

Identifiers

Collections

Citation

F. Andrieu, L. Pirro, R. Berthelon, J. Morgan, G. Cibrario, et al.. Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell V$_T$-mixing. 2018 IEEE Symposium on VLSI Technology and Circuits, Jun 2018, Honolulu, United States. pp.153-154, ⟨10.1109/VLSIT.2018.8510636⟩. ⟨cea-02188622⟩

Share

Metrics

Record views

9