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Compact Modelling of Single Event Transient in Bulk MOSFET for SPICE: Application to Elementary Circuit

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Abstract

Single Event Transients (SET) are important issues concerning reliability of CMOS circuits. They lead to occurrence of soft errors in integrated circuits, such as Single Event Upset (SEU) which consists in unexpected bit state switch in SRAM cells [1,2]. We can find models which describe SET in literature [1, 5] but they are not compact (i e. physical model implemented in Verilog-A). In previous work [6], we proposed a theoretical SET model but the implementation in Verilog-A was still challenging. Here, we describe the implementation in Verilog-A of this model and use it through standard SPICE simulations to study the effect of SET on SRAM cell and shift register.

Dates and versions

cea-02188484 , version 1 (18-07-2019)

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Neil Rostand, Sebastien Martinie, Joris Lacord, Olivier Rozeau, Olivier Billoint, et al.. Compact Modelling of Single Event Transient in Bulk MOSFET for SPICE: Application to Elementary Circuit. SISPAD 2018 - International Conference on Simulation of Semiconductor Processes and Devices, Sep 2018, Austin, United States. pp.364-368, ⟨10.1109/SISPAD.2018.8551633⟩. ⟨cea-02188484⟩
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