Compact Modelling of Single Event Transient in Bulk MOSFET for SPICE: Application to Elementary Circuit
Abstract
Single Event Transients (SET) are important issues concerning reliability of CMOS circuits. They lead to occurrence
of soft errors in integrated circuits, such as Single Event Upset (SEU) which consists in unexpected bit state switch in SRAM cells
[1,2]. We can find models which describe SET in literature [1, 5] but they are not compact (i e. physical model implemented in
Verilog-A). In previous work [6], we proposed a theoretical SET model but the implementation in Verilog-A was still challenging.
Here, we describe the implementation in Verilog-A of this model and use it through standard SPICE simulations to study the effect
of SET on SRAM cell and shift register.