Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications

Gilbert Sassine (1) , Cecile Nail (1) , Luc Tillie (1) , Diego Alfaro Robayo (1) , Alexandre Levisse (1) , Carlo Cagli (1) , Khalil El. Hajjam (1) , Jean-François Nodin (1) , Elisa Vianello (1) , Mathieu Bernard (1) , Gabriel Molas (1) , Etienne Nowak (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

In this paper, programming operations are optimized for low energy consumption and short latency time applications in RRAM kb arrays. Origin of consumption (role of pulse’s time, programming current and voltage in SET and RESET operations) is quantified on HfO$_2$ oxide based RRAM technology. Specific patterns are evaluated to reduce latency time and energy consumption in memory devices. Innovative circuit with $on\ the\ fly$ switching detection is proposed, allowing to reduce programming consumption down to single pJ operation in large memory arrays.

Mots clés: Energy consumption; latency time; RRAM; smart programming

Domaines: Sciences de l'ingénieur [physics]

Gilbert Sassine, Cecile Nail, Luc Tillie, Diego Alfaro Robayo, Alexandre Levisse, et al.. Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications. 2018 IEEE International Reliability Physics Symposium (IRPS), Mar 2018, Burlingame, United States. pp.P-MY.2-1-P-MY.2-5, ⟨10.1109/IRPS.2018.8353675⟩. ⟨cea-02187729⟩