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A Sub-35 pW Axon-Hillock artificial neuron circuit

Abstract : Artificial Intelligence (AI) applications are developing at a high rate, facing soon a tremendous energy challenge. In this context, the original Axon-Hillock (AH) Artificial Neuron (AN) has been optimized to achieve ultra-low power (ULP) consumption. The membrane capacitance was taken out, and in order to drastically reduce its power consumption, the (feedback) capacitance is lowered to 5 fF, the transistors gate width is reduced to 120 nm and the supply voltage is decreased to as low as 200 mV. Designed and fabricated using 65 nm CMOS Technology, the refined AH neuron features a standby power of 11 pW, and when excited, a power consumption that does not exceed 30 pW for a firing frequency of 15.6 kHz. Its energy efficiency per spike is lower than 2 fJ/spike when the DC power is included (around 1 fJ/spike excluding the DC power), for an area of 31 mu m(2). These performance confer to this ULP AH neuron a high potential for future development of highly energy efficient Spiking Neural Networks, required to design future neuroprocessors embedded in various applications (smart visual sensors for autonomous vehicles, robotics).
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https://hal-cea.archives-ouvertes.fr/cea-02186484
Contributor : Marianne Leriche <>
Submitted on : Wednesday, July 17, 2019 - 12:22:52 PM
Last modification on : Tuesday, November 24, 2020 - 2:18:15 PM

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F. Danneville, C. Loyez, K. Carpentier, I Sourikopoulos, E. Mercier, et al.. A Sub-35 pW Axon-Hillock artificial neuron circuit. Solid-State Electronics, Elsevier, 2019, 153, pp.88-92. ⟨10.1016/j.sse.2019.01.002⟩. ⟨cea-02186484⟩

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