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Journal Articles IEEE Transactions on Circuits and Systems I: Regular Papers Year : 2019

Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

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Abstract

This paper proposes a holistic approach that addresses both the message mapping in memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) decoders. We consider a layered hardware architecture using single read/single write port memory banks. The throughput of such an architecture is limited by memory access conflicts, due to improper message mapping in the memory banks, and by pipeline data hazards, due to delayed update effect. We solve these issues hy 1) a residue-based layered scheduling that reduces the pipeline related hazards and 2) off-line algorithms for optimizing the message mapping in memory banks and the message read access scheduling. Our estimates for different LDPC codes indicate that the hardware usage efficiency of our layered decoder is improved by 3%-49% when only the off-line algorithms are employed and by 16%-57% when both the residue-based layered architecture and the off-line algorithms are used.
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Dates and versions

cea-02186481 , version 1 (17-07-2019)

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Oana Boncalo, Gyorgy Kolumban-Antal, Alexandru Amaricai, Valentin Savin, David Declercq. Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66 (4), pp.1643-1656. ⟨10.1109/TCSI.2018.2884252⟩. ⟨cea-02186481⟩
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