212-Gbit/s 2:1 multiplexing selector realised in InP DHBT

A. Konczykowska (1, 2) , F. Jorge (1, 2) , M. Riet (1, 2) , V. Nodjiadjim (1, 2) , B. Duval (1, 2) , H. Mardoyan (1) , J. M. Estaran (1) , A. Adamiecki (1) , G. Raybon (1) , J. -Y. Dupuy (1, 2)

1 Nokia Bell Labs [Nozay]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

In this Letter, the authors report on the design, optimisation and electrical measurements of a new fully integrated multiplexing selector fabricated in 0.7-mu m indium phosphide (InP) double-heterojunction bipolar transistor technology. All parts of the circuit were optimised to obtain 200-Gbit/s class of operation. They present electrical performances at 140 and to a record speed of 212 Gbit/s, highlighting their respective measurement challenges. The power consumption of the circuit is 0.5 and 0.8 W for a differential output amplitude of 240 and 730 mV, respectively. This selector has been successfully used as modulator driver in optical transmission experiments up to 204 Gbit/s.

Domaines: Sciences de l'ingénieur [physics]

A. Konczykowska, F. Jorge, M. Riet, V. Nodjiadjim, B. Duval, et al.. 212-Gbit/s 2:1 multiplexing selector realised in InP DHBT. Electronics Letters, 2019, 55 (5), pp.242-243. ⟨10.1049/el.2018.7545⟩. ⟨cea-02186471⟩