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A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

Abstract : This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip.
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https://hal-cea.archives-ouvertes.fr/cea-02186449
Contributor : Marianne Leriche <>
Submitted on : Wednesday, July 17, 2019 - 12:21:33 PM
Last modification on : Thursday, June 11, 2020 - 5:04:10 PM

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Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, et al.. A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2019, 54 (4), pp.1096-1105. ⟨10.1109/JSSC.2018.2886325⟩. ⟨cea-02186449⟩

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