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Conference papers
Phase-Change Memory: Performance, Roles and Challenges
G. Navarro
1
G. Bourgeois
1
J. Kluge
1
A. L. Serra
1
A. Verdy
1
J. Garrione
1
M. C. Cyrille
1
N. Bernier
1
A. Jannaud
1
C. Sabbione
1
M. Bernard
1
E. Nolot
1
F. Fillot
1
P. Noé
1
L. Fellouh
1
G. Rodriguez
1
V. Beugin
1
O. Cueto
1
N. Castellani
1
J. Coignus
1
V. Delaye
1
C. Socquet-Clerc
1
T. Magis
1
C. Boixaderas
1
S. Barnola
1
E. Nowak
1
S. Barnola 1
Author
E. Nowak 1
Author
1
CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)
- DRT (CEA) - Direction de Recherche Technologique (CEA) : DRT (France)
- CEA - Commissariat à l'énergie atomique et aux énergies alternatives : DRT (Centre de Saclay Centre de Grenoble Centre de Cadarache etc - France)
Abstract : In this paper we analyze recent progress in Phase-Change Memory (PCM) technology targeting both Storage Class Memory and embedded applications. The challenge to achieve a high temperature data retention without compromising the device programming speed can be addressed by material engineering. We show that volume and thermal confinement improvement of the phase-change material enables a high (10-fold) reduction of the programming current, achieved also by the optimization of the device architecture, in particular in the case of a confined structure. It leads to a higher cell efficiency proven by a 6x reduction of the programming current density wrt a standard PCM structure. Furthermore, we demonstrate the reduction of thermal losses by the tuning of the thermal conductivity of the dielectrics surrounding the phase-change material. Finally, we propose some considerations about the PCM ultimate scaling and the reliability at such dimensions, showing that the engineering of the bottom electrode/phase-change material interface can lead to a reduced variability in scaled devices.
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Conference papers
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https://hal-cea.archives-ouvertes.fr/cea-02185419
Contributor : Bruno Savelli <>
Submitted on : Tuesday, July 16, 2019 - 4:03:29 PM
Last modification on : Thursday, June 11, 2020 - 5:04:08 PM
Contributor : Bruno Savelli <>
Submitted on : Tuesday, July 16, 2019 - 4:03:29 PM
Last modification on : Thursday, June 11, 2020 - 5:04:08 PM
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- HAL Id : cea-02185419, version 1
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G. Navarro, G. Bourgeois, J. Kluge, A. L. Serra, A. Verdy, et al.. Phase-Change Memory: Performance, Roles and Challenges. 2018 IEEE International Memory Workshop (IMW), May 2018, Kyoto, Japan. ⟨cea-02185419⟩
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