1μm Pitch direct hybrid bonding with <300nm wafer-to-wafer overlay accuracy

A. Jouve (1) , V. Balan (1) , N. Bresson , C. Euvrard-Colnat (1) , F. Fournel (1) , Y. Exbrayat (1) , G. Mauguen (1) , M. Abdel Sater (1) , C. Beitia (1) , L. Arnaud (1) , S. Cheramy (1) , S. Lhostis (2) , A. Farcy (2) , S. Guillaumet (2) , S. Mermoz (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]

Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since 2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles [1,2] as well as commercial products [3] integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.

Keywords: Copper; Bonding; Surface topography; Rough surfaces; Surface roughness; Surface treatment

Domains: Engineering Sciences [physics]

A. Jouve, V. Balan, N. Bresson, C. Euvrard-Colnat, F. Fournel, et al.. 1μm Pitch direct hybrid bonding with <300nm wafer-to-wafer overlay accuracy. 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2017, Burlingame, Canada. pp.1-2, ⟨10.1109/S3S.2017.8309213⟩. ⟨cea-02185349⟩