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Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics

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Abstract

This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bonded between two wafers of semiconductor devices enabling the 3D power module integration by the 3D stacking of one or multiple switching cells. Specific technology developments are introduced, practical realizations of the concept are presented and the electrical characterizations of the first prototypes are discussed
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Dates and versions

cea-02185324 , version 1 (16-07-2019)

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Kremena Vladimirova, Julie Widiez, Bastien Letowski, Pierre Perreau, Gregory Enyedi, et al.. Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics. 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, France. pp.1251-1257, ⟨10.1109/ECTC.2018.00193⟩. ⟨cea-02185324⟩
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