A Novel Structure for Backside Protection Against Physical Attacks on Secure Chips or SiP

S. Borel (1) , L. Duperrex (1) , E. Deschaseaux (1) , J. Charbonnier (1) , J. Clédière (1) , R. Wacquez (2, 1) , J. Fournier (1) , J. Souriau (1) , Grégory Simon (1) , A. Merle (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 DSUD - CEA Tech en région Sud

A structure intended to protect Integrated Circuits (IC) against physical attacks is presented. Located on the backside of a chip, it complements the countermeasures usually available on the front side of secure components. It aims at preventing attacks such as fault injection by laser illumination and can trigger an alert in case of invasive attacks by circuit edit or micro-probing. Weakening structures have been designed so as to cause the breakage of the die in case of thinning, and a metallic serpentine used as an attack witness has been thought with a maximal complexity so that an attacker cannot skirt it. These elements can be fabricated using standard packaging techniques in a wafer level integration, whether at chip or system scale. The concept of a secure System in Package (SiP) using unsecured chips is proposed, opening the perspective of components fully "secured by packaging".

Mots clés: cybersecurity; backside; 3D integration; wafer level packaging; secure SiP

Domaines: Sciences de l'ingénieur [physics]

S. Borel, L. Duperrex, E. Deschaseaux, J. Charbonnier, J. Clédière, et al.. A Novel Structure for Backside Protection Against Physical Attacks on Secure Chips or SiP. 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. pp.515-520, ⟨10.1109/ECTC.2018.00081⟩. ⟨cea-02185285⟩