Local lateral integration of 16-nm thick Ge nanowires on silicon on insulator substrates

Rami Khazaka (1) , Yann Bogumilowicz (1) , Anne-Marie Papon (1) , Hugo Dansas (1) , Hervé Boutry (1) , Zdenek Chalupa (1) , Valérie Lapras (1) , Bernard Previtali (1) , Sylvain Maitrejean (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

In this contribution, we report on the growth of horizontal Ge nanowires inside extremely thin tunnels surrounded by oxide. This is achieved through selective lateral growth of Ge on silicon-on-insulator (001) substrates. The 16 nm high tunnels are formed by HCl vapor etching of Si followed by Ge growth in the same epitaxy chamber. First, the benefit of growing the Ge nanowires at high temperature was highlighted to homogenize the length of the nanowires and achieve a high growth rate. Afterwards, we showed that increasing the tunnel depth led to a significant reduction in the growth rate. Finally, transmission electron microscopy showed that no defects were present in the Ge nanowires. These results are encouraging for the planar co-integration of heterogeneous materials on Si.

Domains: Engineering Sciences [physics]

Rami Khazaka, Yann Bogumilowicz, Anne-Marie Papon, Hugo Dansas, Hervé Boutry, et al.. Local lateral integration of 16-nm thick Ge nanowires on silicon on insulator substrates. Applied Physics Letters, 2018, 112 (24), pp.241602. ⟨10.1063/1.5034205⟩. ⟨cea-02185226⟩