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Journal Articles Physical Review Applied Year : 2018

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell


Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element LC resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of $\delta$$q$ = 95 × 10$^{−6} e$ Hz$^{-1/2}$ when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.
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cea-02184791 , version 1 (16-07-2019)



S. Schaal, S. Barraud, J.  J. l. Morton, M. F. Gonzalez-Zalba. Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell. Physical Review Applied, 2018, 9 (5), pp.054016. ⟨10.1103/PhysRevApplied.9.054016⟩. ⟨cea-02184791⟩
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