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Journal Articles Solid-State Electronics Year : 2018

Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs

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Abstract

This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (I$_{DS}$) varying the back gate bias (V$_B$), aiming the extraction of carriers' mobility of each level separately. The methodology consists of three main steps and accounts for V$_B$ influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying V$_B$ through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V$_B$ for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of V$_B$ and up to 150°C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.
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Dates and versions

cea-01974229 , version 1 (08-01-2019)

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Bruna Cardoso Paz, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs. Solid-State Electronics, 2018, 149, pp.62-70. ⟨10.1016/j.sse.2018.08.012⟩. ⟨cea-01974229⟩
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