Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs

Abstract : This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (I$_{DS}$) varying the back gate bias (V$_B$), aiming the extraction of carriers' mobility of each level separately. The methodology consists of three main steps and accounts for V$_B$ influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying V$_B$ through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V$_B$ for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of V$_B$ and up to 150°C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.
Type de document :
Article dans une revue
Solid-State Electronics, Elsevier, 2018, 149, pp.62-70. 〈10.1016/j.sse.2018.08.012〉
Liste complète des métadonnées

https://hal-cea.archives-ouvertes.fr/cea-01974229
Contributeur : Sylvain Barraud <>
Soumis le : mardi 8 janvier 2019 - 16:28:20
Dernière modification le : lundi 11 février 2019 - 16:49:01

Fichier

12-PAZ_SSE_2018.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

Collections

Citation

Bruna Cardoso Paz, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs. Solid-State Electronics, Elsevier, 2018, 149, pp.62-70. 〈10.1016/j.sse.2018.08.012〉. 〈cea-01974229〉

Partager

Métriques

Consultations de la notice

27

Téléchargements de fichiers

17