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Journal Articles Solid-State Electronics Year : 2018

Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

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Abstract

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [110]-and [100]-oriented channels, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [110]-in comparison to [100]-oriented NWs due to higher holes mobility contribution in (110) plan. Improvements obtained on I$_{ON}$/I$_{OFF}$ by reducing W$_{FIN}$ are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [110]-and [100]-oriented NWs, respectively.
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Dates and versions

cea-01974222 , version 1 (08-01-2019)

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Bruna Cardoso Paz, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. Electrical Characterization of Vertically Stacked p-FET SOI Nanowires. Solid-State Electronics, 2018, 141, pp.84-91. ⟨10.1016/j.sse.2017.12.011⟩. ⟨cea-01974222⟩
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