Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz; Mikael Casse; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot; Marcelo Pavanello

doi:10.1016/j.sse.2017.12.011

Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz ¹ Mikael Casse ² Sylvain Barraud ² Gilles Reimbold ² Maud Vinet ² Olivier Faynot ² Marcelo Pavanello ¹

1 Department of Electrical Engineering

2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information

Abstract : This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [110]-and [100]-oriented channels, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [110]-in comparison to [100]-oriented NWs due to higher holes mobility contribution in (110) plan. Improvements obtained on I$_{ON}$/I$_{OFF}$ by reducing W$_{FIN}$ are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [110]-and [100]-oriented NWs, respectively.

Keywords : electrical characterization transport performance vertically stacked nanowire SOI MOSFET channel orientation

Document type :

Journal articles

Domain :

Engineering Sciences [physics]

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

Liste complète des métadonnées

https://hal-cea.archives-ouvertes.fr/cea-01974222
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 4:26:38 PM
Last modification on : Monday, February 25, 2019 - 4:34:22 PM

11-Paz_SSE_2017.pdf

Files produced by the author(s)

Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

File

Identifiers

Collections

Citation

Export

Metrics

23

32

Contact

Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

File

Identifiers

Collections

Citation

Export

Share

Metrics

23

32

Contact