Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz (1) , Mikael Casse (2) , Sylvain Barraud (2) , Gilles Reimbold (2) , Maud Vinet (2) , Olivier Faynot (2) , Marcelo Antonio Pavanello (1)

1 Department of Electrical Engineering
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [110]-and [100]-oriented channels, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [110]-in comparison to [100]-oriented NWs due to higher holes mobility contribution in (110) plan. Improvements obtained on I$_{ON}$/I$_{OFF}$ by reducing W$_{FIN}$ are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [110]-and [100]-oriented NWs, respectively.

Keywords: performance; transport; electrical characterization; vertically stacked nanowire; SOI MOSFET; channel orientation

Domains: Engineering Sciences [physics]; Engineering Sciences [physics]; Micro and nanotechnologies/Microelectronics

Bruna Cardoso Paz, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. Electrical Characterization of Vertically Stacked p-FET SOI Nanowires. Solid-State Electronics, 2018, 141, pp.84-91. ⟨10.1016/j.sse.2017.12.011⟩. ⟨cea-01974222⟩