Electrical Characterization of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz 1 Mikael Casse 2 Sylvain Barraud 2 Gilles Reimbold 2 Maud Vinet 2 Olivier Faynot 2 Marcelo Pavanello 1
1 Department of Electrical Engineering
2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
Abstract : This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [110]-and [100]-oriented channels, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [110]-in comparison to [100]-oriented NWs due to higher holes mobility contribution in (110) plan. Improvements obtained on I$_{ON}$/I$_{OFF}$ by reducing W$_{FIN}$ are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [110]-and [100]-oriented NWs, respectively.
Keywords : electrical characterization transport performance vertically stacked nanowire SOI MOSFET channel orientation
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Article dans une revue
Solid-State Electronics, Elsevier, 2018, 141, pp.84-91. 〈10.1016/j.sse.2017.12.011〉
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https://hal-cea.archives-ouvertes.fr/cea-01974222
Contributeur : Sylvain Barraud <>
Soumis le : mardi 8 janvier 2019 - 16:26:38
Dernière modification le : lundi 11 février 2019 - 16:46:00

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Bruna Cardoso Paz, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. Electrical Characterization of Vertically Stacked p-FET SOI Nanowires. Solid-State Electronics, Elsevier, 2018, 141, pp.84-91. 〈10.1016/j.sse.2017.12.011〉. 〈cea-01974222〉

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