J. Colinge, Multiple-gate SOI MOSFETs, Solid-State Electron, vol.48, issue.6, pp.897-905, 2004.
DOI : 10.1016/j.sse.2003.12.020

URL : https://hal.archives-ouvertes.fr/hal-00603741

K. J. Kuhn, Considerations for Ultimate CMOS Scaling, IEEE Trans. Electron Devices, vol.59, issue.7, pp.1813-1828, 2012.

R. Coquand, Strain-induced performance enhancement of trigate and omega-gate nanowire FETs scaled down to 10nm Width, 2012 Symposium on VLSI Technology (VLSIT), pp.13-14, 2012.
URL : https://hal.archives-ouvertes.fr/hal-01017518

R. Coquand, Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS), pp.37-40, 2012.

S. Barraud, Strained Silicon Directly on Insulator N-and PFET nanowire transistors, 2014 15th International Conference on Ultimate Integration on Silicon, pp.65-68, 2014.

M. Saitoh, Short-channel performance and mobility analysis of <110>-and <100>-oriented tri-gate nanowire MOSFETs with raised source/drain extensions, 2010 Symposium on VLSI Technology, pp.169-170, 2010.

H. Mertens, Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates, 2016 IEEE Symposium on VLSI Technology, pp.1-2, 2016.

C. Dupre, 15nm-diameter 3D stacked nanowires with independent gates operation: ?FET, 2008 IEEE International Electron Devices Meeting, pp.1-4, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00392154

S. Barraud, Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain, 2016 IEEE International Electron Devices Meeting (IEDM), pp.17-23, 2016.
URL : https://hal.archives-ouvertes.fr/cea-01973383

S. Takagi, A. Toriumi, M. Iwase, and H. Tango, On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation, IEEE Trans. Electron Devices, vol.41, issue.12, pp.2363-2368, 1994.

J. Pelloux-prayer, Study of the piezoresistive properties of NMOS and PMOS ?-gate SOI nanowire transistors: Scalability effects and high stress level, Electron Devices Meeting (IEDM), 2014.
URL : https://hal.archives-ouvertes.fr/hal-02138872

G. Ghibaudo, New method for the extraction of MOSFET parameters, Electron. Lett, vol.24, issue.9, pp.543-545, 1988.
URL : https://hal.archives-ouvertes.fr/jpa-00227914

A. Ohata, M. Cassé, and S. Cristoloveanu, Front-and back-channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method, Solid-State Electron, vol.51, issue.2, pp.245-251, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00393599

J. Pelloux-prayer, Transport in TriGate nanowire FET: Crosssection effect at the nanometer scale, 2016 IEEE SOI-3DSubthreshold Microelectronics Technology Unified Conference, pp.1-2, 2016.
URL : https://hal.archives-ouvertes.fr/hal-02143469