Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz (1) , Marcelo Antonio Pavanello (1) , Mikael Casse (2) , Sylvain Barraud (2) , Gilles Reimbold (2) , Maud Vinet (2) , Olivier Faynot (2)

1 Department of Electrical Engineering
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution.

Mots clés: electrical characterization; vertically stacked nanowire; transport; performance; SOI MOSFET; channel orientation

Domaines: Sciences de l'ingénieur [physics]; Electronique

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikael Casse, Sylvain Barraud, Gilles Reimbold, et al.. Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athènes, Greece. ⟨10.1109/ULIS.2017.7962606⟩. ⟨cea-01974216⟩