Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz; Marcelo Pavanello; Mikael Casse; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot

Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires

Bruna Cardoso Paz ^{1, *} Marcelo Pavanello ¹ Mikael Casse ² Sylvain Barraud ² Gilles Reimbold ² Maud Vinet ² Olivier Faynot ²

* Corresponding author

1 Department of Electrical Engineering

2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information

Abstract : This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution.

Keywords : performance SOI MOSFET channel orientation transport vertically stacked nanowire electrical characterization

Document type :

Conference papers

Domain :

Engineering Sciences [physics]

Engineering Sciences [physics] / Electronics

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