Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires

Abstract : This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (W$_{FIN}$) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution.
Document type :
Conference papers
Complete list of metadatas

Cited literature [10 references]  Display  Hide  Download

https://hal-cea.archives-ouvertes.fr/cea-01974216
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 4:25:21 PM
Last modification on : Monday, February 25, 2019 - 4:34:22 PM

File

9-Cardoso_ULIS_2017.pdf
Files produced by the author(s)

Identifiers

Collections

Citation

Bruna Cardoso Paz, Marcelo Pavanello, Mikael Casse, Sylvain Barraud, Gilles Reimbold, et al.. Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athènes, Greece. ⟨10.1109/ULIS.2017.7962606⟩. ⟨cea-01974216⟩

Share

Metrics

Record views

37

Files downloads

87