New method for individual electrical characterization of stacked SOI nanowire MOSFETs

Bruna Cardoso Paz 1, * Mikaël Cassé 2 Sylvain Barraud 2 Gilles Reimbold 2 Maud Vinet 2 Olivier Faynot 2 Marcelo Pavanello 1
* Auteur correspondant
1 Centro Universitário FEI
2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
Abstract : A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom -NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
Keywords : stacked nanowires mobility back gate bias SOI
Type de document :
Communication dans un congrès
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2017, Burlingame, United States. 〈10.1109/S3S.2017.8309237〉
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https://hal-cea.archives-ouvertes.fr/cea-01974212
Contributeur : Sylvain Barraud <>
Soumis le : mardi 8 janvier 2019 - 16:23:45
Dernière modification le : lundi 25 février 2019 - 16:34:22

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Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. New method for individual electrical characterization of stacked SOI nanowire MOSFETs. 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2017, Burlingame, United States. 〈10.1109/S3S.2017.8309237〉. 〈cea-01974212〉

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