New method for individual electrical characterization of stacked SOI nanowire MOSFETs

Bruna Cardoso Paz (1) , Mikaël Cassé (2) , Sylvain Barraud (2) , Gilles Reimbold (2) , Maud Vinet (2) , Olivier Faynot (2) , Marcelo Antonio Pavanello (1)

1 Centro Universitário FEI
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom -NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.

Keywords: stacked nanowires; mobility; back gate bias; SOI

Domains: Engineering Sciences [physics]; Engineering Sciences [physics]; Electronics

Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, et al.. New method for individual electrical characterization of stacked SOI nanowire MOSFETs. 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2017, Burlingame, United States. ⟨10.1109/S3S.2017.8309237⟩. ⟨cea-01974212⟩