Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs

S. Barraud (1) , V. Lapras (1) , B. Previtali (1) , M. Samson (2) , J. Lacord (1) , S. Martinie (1) , M.-A Jaud (1) , S Athanasiou (1) , F. Triozon (1) , O. Rozeau (1) , J M Hartmann (1) , C Vizioz (1) , C Comboroure (2) , F Andrieu (1) , J C Barbé (1) , M Vinet (1) , T Ernst (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]

This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.

Domains: Engineering Sciences [physics]

S. Barraud, V. Lapras, B. Previtali, M. Samson, J. Lacord, et al.. Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs. 2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. ⟨10.1109/IEDM.2017.8268473⟩. ⟨cea-01973409⟩