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Conference papers
Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs
S. Barraud
1, *
V. Lapras
1
B. Previtali
1
M. Samson
2
J. Lacord
1
S. Martinie
1
M.-A Jaud
1
S Athanasiou
1
F. Triozon
1
O. Rozeau
1
J Hartmann
1
C Vizioz
1
C Comboroure
2
F Andrieu
1
J Barbé
1
M Vinet
1
T Ernst
1
S. Barraud 1
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Correspondent author
V. Lapras 1
Author
B. Previtali 1
Author
M. Samson 2
Author
T Ernst 1
Author
1
CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)
- UGA - Université Grenoble Alpes (CS 40700 - 38058 Grenoble cedex - France)
- DRT (CEA) - Direction de Recherche Technologique (CEA) : DRT (France)
- CEA - Commissariat à l'énergie atomique et aux énergies alternatives : DRT (Centre de Saclay Centre de Grenoble Centre de Cadarache etc - France)
2
ST-CROLLES - STMicroelectronics [Crolles] (850 rue Jean Monnet BP 16 38926 Crolles - France)
Abstract : This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.
Domain :
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https://hal-cea.archives-ouvertes.fr/cea-01973409
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:14 PM
Last modification on : Monday, April 6, 2020 - 9:22:34 AM
Document(s) archivé(s) le : Tuesday, April 9, 2019 - 3:08:12 PM
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:14 PM
Last modification on : Monday, April 6, 2020 - 9:22:34 AM
Document(s) archivé(s) le : Tuesday, April 9, 2019 - 3:08:12 PM
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6-Barraud_IEDM2017.pdf
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Identifiers
- HAL Id : cea-01973409, version 1
- DOI : 10.1109/IEDM.2017.8268473
Citation
S. Barraud, V. Lapras, B. Previtali, M. Samson, J. Lacord, et al.. Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs. 2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. ⟨10.1109/IEDM.2017.8268473⟩. ⟨cea-01973409⟩
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