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Conference papers
Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs
Abstract : This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.
Cited literature [3 references]
https://hal-cea.archives-ouvertes.fr/cea-01973409
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:14 PM
Last modification on : Monday, December 14, 2020 - 3:38:32 PM
Long-term archiving on: : Tuesday, April 9, 2019 - 3:08:12 PM
Contributor : Sylvain Barraud <>
Submitted on : Tuesday, January 8, 2019 - 12:05:14 PM
Last modification on : Monday, December 14, 2020 - 3:38:32 PM
Long-term archiving on: : Tuesday, April 9, 2019 - 3:08:12 PM
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6-Barraud_IEDM2017.pdf
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