NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

O. Rozeau (1) , S. Martinie (1) , T. Poiroux (1) , F. Triozon (1) , S. Barraud (1) , J. Lacord (1) , Y. M. Niquet (2) , C. Tabone (1) , R. Coquand (1) , E. Augendre (1) , M. Vinet (1) , O. Faynot (1) , J.-Ch Barbé (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 LSIM - Laboratory of Atomistic Simulation

In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confinement, this model is able to handle arbitrary NW/NS cross-section shape of stacked-planar and vertical GAA MOSFETs (circular, square, rectangular). This Nanowire Surface Potential (NSP) based model, validated both by numerical simulations and experimental data, is demonstrated to be very accurate in all operation regimes of GAA MOSFETs.

Domains: Engineering Sciences [physics]

O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, et al.. NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs. 2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. ⟨10.1109/IEDM.2016.7838369⟩. ⟨cea-01973390⟩