Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

Abstract : We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.
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Communication dans un congrès
2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. 〈10.1109/IEDM.2016.7838441〉
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https://hal-cea.archives-ouvertes.fr/cea-01973383
Contributeur : Sylvain Barraud <>
Soumis le : mardi 8 janvier 2019 - 11:59:26
Dernière modification le : lundi 11 février 2019 - 16:48:02

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S. Barraud, V. Lapras, M. Samson, L Gaben, L. Grenouillet, et al.. Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain. 2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. 〈10.1109/IEDM.2016.7838441〉. 〈cea-01973383〉

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