Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

S. Barraud (1, 2) , V. Lapras (2) , M. P. Samson (3) , L Gaben (2, 3) , L. Grenouillet (2) , V Maffini-Alvaro (2) , Y. Morand (3) , J Daranlot (2) , N. Rambal (2) , B Previtalli (2) , S Reboh (2) , C Tabone (2) , R Coquand (2) , E Augendre (2) , O Rozeau (2) , J M Hartmann (2) , C Vizioz (2) , C Arvet (3) , P Pimenta-Barros (2) , N Posseme (2) , V Loup (2) , C Comboroure (3) , C Euvrard (2) , V Balan (2) , I Tinti (2) , G Audoit (2) , N Bernier (2) , D Cooper (2) , Z Saghi (2) , F Allain (2) , A Toffoli (2) , O Faynot (2) , M Vinet (2)

1 LGCIE - Laboratoire de Génie Civil et d'Ingénierie Environnementale
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 ST-CROLLES - STMicroelectronics [Crolles]

We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.

Domains: Engineering Sciences [physics]

S. Barraud, V. Lapras, M. P. Samson, L Gaben, L. Grenouillet, et al.. Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain. 2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. ⟨10.1109/IEDM.2016.7838441⟩. ⟨cea-01973383⟩