Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain - Archive ouverte HAL Access content directly
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Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

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Abstract

We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.
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Dates and versions

cea-01973383 , version 1 (08-01-2019)

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S. Barraud, V. Lapras, M. P. Samson, L Gaben, L. Grenouillet, et al.. Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain. 2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. ⟨10.1109/IEDM.2016.7838441⟩. ⟨cea-01973383⟩
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